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<title>CMSIS-Core (Cortex-A): L2C_310_TypeDef Struct Reference</title>
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   <div id="projectname">CMSIS-Core (Cortex-A)
   &#160;<span id="projectnumber">Version 1.1.4</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<div class="header">
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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">L2C_310_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group__L2__cache__functions.html">L2C-310 Cache Controller Functions</a></div></div>  </div>
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<p>Union type to access the L2C_310 Cache Controller.  
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a87833c2acdf685d6ad6d0811f45677d7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a87833c2acdf685d6ad6d0811f45677d7">CACHE_ID</a></td></tr>
<tr class="memdesc:a87833c2acdf685d6ad6d0811f45677d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0000 (R/ ) Cache ID Register.  <a href="#a87833c2acdf685d6ad6d0811f45677d7">More...</a><br/></td></tr>
<tr class="separator:a87833c2acdf685d6ad6d0811f45677d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af19e1fd8a729834557884232c9e50bd2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#af19e1fd8a729834557884232c9e50bd2">CACHE_TYPE</a></td></tr>
<tr class="memdesc:af19e1fd8a729834557884232c9e50bd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0004 (R/ ) Cache Type Register.  <a href="#af19e1fd8a729834557884232c9e50bd2">More...</a><br/></td></tr>
<tr class="separator:af19e1fd8a729834557884232c9e50bd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a491a4ed1ecdcdf784b180fa13ef46f2f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a491a4ed1ecdcdf784b180fa13ef46f2f">CONTROL</a></td></tr>
<tr class="memdesc:a491a4ed1ecdcdf784b180fa13ef46f2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0100 (R/W) Control Register.  <a href="#a491a4ed1ecdcdf784b180fa13ef46f2f">More...</a><br/></td></tr>
<tr class="separator:a491a4ed1ecdcdf784b180fa13ef46f2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4f7bc7277a5baa1d804913e41b8200be"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a4f7bc7277a5baa1d804913e41b8200be">AUX_CNT</a></td></tr>
<tr class="memdesc:a4f7bc7277a5baa1d804913e41b8200be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0104 (R/W) Auxiliary Control.  <a href="#a4f7bc7277a5baa1d804913e41b8200be">More...</a><br/></td></tr>
<tr class="separator:a4f7bc7277a5baa1d804913e41b8200be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2bc6f09ea83f8d3c966558598a098995"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a2bc6f09ea83f8d3c966558598a098995">EVENT_CONTROL</a></td></tr>
<tr class="memdesc:a2bc6f09ea83f8d3c966558598a098995"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0200 (R/W) Event Counter Control.  <a href="#a2bc6f09ea83f8d3c966558598a098995">More...</a><br/></td></tr>
<tr class="separator:a2bc6f09ea83f8d3c966558598a098995"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4465c7dd7b45f8f35acde8c6e28cbd17"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a4465c7dd7b45f8f35acde8c6e28cbd17">EVENT_COUNTER1_CONF</a></td></tr>
<tr class="memdesc:a4465c7dd7b45f8f35acde8c6e28cbd17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0204 (R/W) Event Counter 1 Configuration.  <a href="#a4465c7dd7b45f8f35acde8c6e28cbd17">More...</a><br/></td></tr>
<tr class="separator:a4465c7dd7b45f8f35acde8c6e28cbd17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c78032b2b237ee968d6758bddc915ba"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a1c78032b2b237ee968d6758bddc915ba">EVENT_COUNTER0_CONF</a></td></tr>
<tr class="memdesc:a1c78032b2b237ee968d6758bddc915ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0208 (R/W) Event Counter 1 Configuration.  <a href="#a1c78032b2b237ee968d6758bddc915ba">More...</a><br/></td></tr>
<tr class="separator:a1c78032b2b237ee968d6758bddc915ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c8ff2c17c6f3eb0d951e4cd193fd8e4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a7c8ff2c17c6f3eb0d951e4cd193fd8e4">INTERRUPT_MASK</a></td></tr>
<tr class="memdesc:a7c8ff2c17c6f3eb0d951e4cd193fd8e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0214 (R/W) Interrupt Mask.  <a href="#a7c8ff2c17c6f3eb0d951e4cd193fd8e4">More...</a><br/></td></tr>
<tr class="separator:a7c8ff2c17c6f3eb0d951e4cd193fd8e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a207e1eb35e13440241db1109790d9740"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a207e1eb35e13440241db1109790d9740">MASKED_INT_STATUS</a></td></tr>
<tr class="memdesc:a207e1eb35e13440241db1109790d9740"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0218 (R/ ) Masked Interrupt Status.  <a href="#a207e1eb35e13440241db1109790d9740">More...</a><br/></td></tr>
<tr class="separator:a207e1eb35e13440241db1109790d9740"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a404f8453b6df3aaf5f3db4ff9b658637"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a404f8453b6df3aaf5f3db4ff9b658637">RAW_INT_STATUS</a></td></tr>
<tr class="memdesc:a404f8453b6df3aaf5f3db4ff9b658637"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x021c (R/ ) Raw Interrupt Status.  <a href="#a404f8453b6df3aaf5f3db4ff9b658637">More...</a><br/></td></tr>
<tr class="separator:a404f8453b6df3aaf5f3db4ff9b658637"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43116dfea74e77e870fd790189a403ec"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a43116dfea74e77e870fd790189a403ec">INTERRUPT_CLEAR</a></td></tr>
<tr class="memdesc:a43116dfea74e77e870fd790189a403ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0220 ( /W) Interrupt Clear.  <a href="#a43116dfea74e77e870fd790189a403ec">More...</a><br/></td></tr>
<tr class="separator:a43116dfea74e77e870fd790189a403ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9b9d1842b5d9e828a6825533ab80c0f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#ab9b9d1842b5d9e828a6825533ab80c0f">CACHE_SYNC</a></td></tr>
<tr class="memdesc:ab9b9d1842b5d9e828a6825533ab80c0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0730 (R/W) Cache Sync.  <a href="#ab9b9d1842b5d9e828a6825533ab80c0f">More...</a><br/></td></tr>
<tr class="separator:ab9b9d1842b5d9e828a6825533ab80c0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1e7c5255e61ce785f2fd5c767178c098"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a1e7c5255e61ce785f2fd5c767178c098">INV_LINE_PA</a></td></tr>
<tr class="memdesc:a1e7c5255e61ce785f2fd5c767178c098"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0770 (R/W) Invalidate Line By PA.  <a href="#a1e7c5255e61ce785f2fd5c767178c098">More...</a><br/></td></tr>
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<tr class="memdesc:a78853d391272ff835025e8382c3c88d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x077c (R/W) Invalidate by Way.  <a href="#a78853d391272ff835025e8382c3c88d2">More...</a><br/></td></tr>
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<tr class="memdesc:a400d9ededaf12a5193e01d7235f3d65d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x07b0 (R/W) Clean Line by PA.  <a href="#a400d9ededaf12a5193e01d7235f3d65d">More...</a><br/></td></tr>
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<tr class="memdesc:ac79d3397741a3ae8566c878b45d30970"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x07b8 (R/W) Clean Line by Index/Way.  <a href="#ac79d3397741a3ae8566c878b45d30970">More...</a><br/></td></tr>
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<tr class="memdesc:a0e6d40fb25420d5cac5be15ad2662e2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x07bc (R/W) Clean by Way.  <a href="#a0e6d40fb25420d5cac5be15ad2662e2c">More...</a><br/></td></tr>
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<tr class="memdesc:a61615f4a4ac97d5d278000a35100d795"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA.  <a href="#a61615f4a4ac97d5d278000a35100d795">More...</a><br/></td></tr>
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<tr class="memdesc:a6f777080cbf9426d8476d07f6e583d71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0928 (R/W) Data Lockdown 5 by Way.  <a href="#a6f777080cbf9426d8476d07f6e583d71">More...</a><br/></td></tr>
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<tr class="memdesc:a9464799ec7797bacade9eacd4703bad2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x092c (R/W) Instruction Lockdown 5 by Way.  <a href="#a9464799ec7797bacade9eacd4703bad2">More...</a><br/></td></tr>
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<tr class="memdesc:ab81366685e54829cae7613f080d69f53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0930 (R/W) Data Lockdown 5 by Way.  <a href="#ab81366685e54829cae7613f080d69f53">More...</a><br/></td></tr>
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<tr class="memdesc:a990118c9674df74beb6879b3f6dbcbc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way.  <a href="#a990118c9674df74beb6879b3f6dbcbc6">More...</a><br/></td></tr>
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<tr class="memdesc:aed70f16007d4e7d19818e0931581c5a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0938 (R/W) Data Lockdown 6 by Way.  <a href="#aed70f16007d4e7d19818e0931581c5a5">More...</a><br/></td></tr>
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<tr class="memdesc:a6240652959732fbb74bbee91d4b487d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x093c (R/W) Instruction Lockdown 6 by Way.  <a href="#a6240652959732fbb74bbee91d4b487d0">More...</a><br/></td></tr>
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<tr class="memdesc:a58357795f3cda2b0063411abc5165804"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0950 (R/W) Lockdown by Line Enable.  <a href="#a58357795f3cda2b0063411abc5165804">More...</a><br/></td></tr>
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<tr class="memdesc:acb39f337a421d0640f39092dc992ef1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0954 (R/W) Unlock All Lines by Way.  <a href="#acb39f337a421d0640f39092dc992ef1a">More...</a><br/></td></tr>
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<tr class="memdesc:ae3f752040cdfcabd337b3f0359216b11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0c00 (R/W) Address Filtering Start.  <a href="#ae3f752040cdfcabd337b3f0359216b11">More...</a><br/></td></tr>
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<tr class="memdesc:a956e7653f25ae52ac9534eb0e1d94c8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0c04 (R/W) Address Filtering End.  <a href="#a956e7653f25ae52ac9534eb0e1d94c8c">More...</a><br/></td></tr>
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<tr class="memdesc:a996a2a5c1f311a6f3555844adc28e7f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0f40 (R/W) Debug Control Register.  <a href="#a996a2a5c1f311a6f3555844adc28e7f4">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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          <td class="memname">L2C_310_TypeDef::ADDRESS_FILTER_END</td>
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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t L2C_310_TypeDef::ADDRESS_FILTER_START</td>
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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t L2C_310_TypeDef::AUX_CNT</td>
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          <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t L2C_310_TypeDef::CACHE_ID</td>
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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t L2C_310_TypeDef::CACHE_SYNC</td>
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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_INDEX_WAY</td>
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